The present invention relates to the field of the integrated circuit design, and more specifically, to the field of charge pump circuits.
Memory circuits often require the internal generation of boosted voltages that are needed to program, erase or read the individual memory cells. In the prior art, it is well known that a charge pump circuit can be used to boost voltages supplied by an external voltage source, so that the boosted voltages can be used for program, erase or read operations on the individual memory cells. Depending on voltage and current requirements, different pump architectures are needed, in terms of parallel and series stages. During some internal operation modes a plurality of voltage values may be needed on a node boosted by means of a charge pump.
FIG. 1 depicts a simple schematic diagram for a typical charge pump 10 used to generate a supply voltage Vout 12 from a first constant voltage input Vdd 14. Capacitors CP116 and CP218 are alternately held at charge pump clock signal CK 20 and its inverse /CK 22, provided by an external signal CLK 24, which determines the charge transfer rate. A control signal ENA 26, controls the on-off switching of the pump 10. A regulator (not shown) disables the clock CLK 24 and/or the ENA signal 26 once the Vout voltage 12 has reached the desired value, Vref 42, as shown in FIG. 2. Due to the current consumption Vout decreases. Once Vout has reached a fixed value 44 lower than Vref 42, the regulator (not shown) enables the charge pump 10 (of FIG. 1) again. A multiplicity of voltage values can be achieved by increasing the number of diodes/stages from the two stages (D128 and D230), as shown in FIG. 1.
It is well known in the art that demand for current Ipump from an internal regulated voltage Vpump varies depending on the operational state of the memory. As shown in FIG. 3, the current consumption on the output pump node Outp 64 can be sustained by means of 2 charge pumps 66 and 68, properly enabled by control signals ENA172 and ENA274, working in parallel between Vdd 70 and Outp 64, furnishing the same Vpump voltage 76, and furnishing the requested Ipump (not shown).
However, there are two major problems that charge pumps furnishing a plurality of voltage values on a single output node Outp have to address: (1) how to obtain a good efficiency by increasing the Ipump/Isupply ratio, where Isupply is the current consumption from the Vdd voltage supply; and (2) how to reduce the Vr/Vpump ratio, where Vr is the ripple amplitude.
These problems are exacerbated when a low Vpump value has to be obtained on an Outp node of a charge pump including a number of serial stages exceeding the minimum number N needed to obtain the required high Vpump voltage. Indeed, in this example, a significant part of the supply current Isupply is used to charge/discharge the capacitors of the xe2x80x9cuselessxe2x80x9d stages of the pump, so that even if the Ipump requested on the Outp node is low, a huge current consumption from Vdd is observed. For example, the pump that has been previously tuned on a high Vpump value, is now tuned to furnish a lower Vpump value. If this is the case, the same internal nodes of the pump charged at high potential values corresponding to a high Vpump value, have to yield a lower Vpump value without being re-charged to proper potential values corresponding to the desired lower Vpump value. This results is a spurious pumping and in a relatively high ripple voltage Vr on the Outp node, until the steady state is reached.
We have solved the above-mentioned problem by having different pumps working in parallel, as in FIG. 3, but each one furnishing a different voltage and properly enabled. We have provided a modular charge pump structure made of selectable parallel pumps, each one giving a different voltage Vpump, and each one furnishing a desired current Ipump, but without significantly increasing the area of the integrated circuit occupied by this flexible charge pump structure.
The present invention provides a charge pump architecture featuring a modular arrangement of charge pumps. The charge pumps are arranged as a plurality of charge pump stages connected in a plurality of paths between an input node receiving a supply voltage and an output node delivering an output voltage, with pump stages each having an activation line receiving an enabling signal that activates the pump stage. The activation lines are fed by a logic circuit having an arrangement of logic elements simultaneously generating enabling signals corresponding to a desired output voltage. The term xe2x80x9csimultaneous generatingxe2x80x9d includes all phase variants of a pulse, since phase variants are responsible for clocking various pump stages in proper sequence. This allows a number and arrangement of simultaneously selectively activated pump stages to produce a desired output voltage.
One aspect of the present invention is directed to an apparatus comprising a first plurality of parallel-connected blocks of charge pump stages including a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween.
In one embodiment of the present invention, each of the parallel-connected blocks of charge pump stages includes a group of a second plurality of charge pump stages cascade-connected in series; and an output stage connected to an output node.
In one embodiment of the present invention, each of the charge pump stages further comprises: (a) a first switch; (b) a second switch; (c) a boost capacitor electrically communicating with the first switch and the second switch; and (d) an inverter with an output electrically communicating with the boost capacitor and a pumping node. In this embodiment, the inverter having an input receives an enabling clock signal to the boost capacitor, and the first and second switches are operated by clock signals corresponding to the enabling clock signal.
In another embodiment of the present invention, each of the charge pump stage further comprises a positive charge pump. In an alternative embodiment of the present invention, each of the charge pump stages further comprises a negative charge pump.
In another embodiment of the present invention, there is an integer first plurality of P blocks with an integer N of charge pump stages in each block. In this embodiment, a total number T of charge pump stages is equal to NP and a number of output stages is equal to P.
Another aspect of the present invention is directed to an apparatus for generating a supply voltage internally within an integrated circuit comprising an integer plurality of M single (N, P) charge pumps.
In yet another embodiment of the present invention, each single (N, P) charge pump includes an integer P of parallel-connected blocks of charge pump stages comprising a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween.
In another embodiment, each of the parallel-connected blocks of charge pump stages includes a group of an integer N of the charge pump stages cascade-connected in series; and an output stage connected to an output node. In this embodiment, an integer T of total number of charge pump stages is equal to PMN; and an integer O of output stages is equal to PM.
Yet, one more aspect of the present invention is directed to an apparatus for generating a supply voltage internally within an integrated circuit comprising an integer plurality of M single charge pumps, wherein a first single charge pump comprises a single (n1, p1) charge pump, wherein at least one intermediate single charge pump therebetween comprises a single (ni, pi) charge pump, and wherein a last single charge pump comprises a single (nM, pM) charge pump.
In another embodiment of the present invention, each single (ni, pi) charge pump includes a pi integer of parallel-connected blocks of charge pump stages comprising a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween.
In another embodiment, each of the parallel-connected blocks of charge pump stages includes a group of an integer ni number of charge pump stages cascade-connected in series; and an output stage connected to an output node. In this embodiment, an integer O of output stages is equal to xcexa3i=1i=M (pi); and an integer T of total number of charge pump stages is equal to xcexa3i=li=M (ni pi) wherein i is an integer less or equal to M.
In yet another embodiment, in each single (ni, pi) charge pump, ni is greater than or equal to pi. In an alternative embodiment, pi is greater than or equal to ni. Herein, ni is less than or equal to N; and pi is less or equal to P, wherein an integer P is a total number of parallel-connected blocks of charge pump stages, and an integer N is a total number of charge pump stages cascade-connected in series. In one embodiment, an integer S groups of control signals are used to control each charge pump stage, and at least one group of the control signals is used to control the charge pump stage.
In an embodiment of the invention, the apparatus of the present invention comprising the plurality of M single charge pumps, includes an integer plurality of Q1 different configurations of single charge pumps. In a further, for each configuration, each output stage is connected to the output node, an integer plurality of C1 charge pump stages is disabled. The apparatus is adaptively tuned among the plurality of Q1 different configurations by using a plurality of control signals in order to optimize generation of the supply voltage and supply current at the output node, and to minimize a ripple voltage at the output node.
One additional aspect of the present invention is directed to an apparatus for generating a supply voltage internally within an integrated circuit comprising an integer plurality of M single charge pumps, and an auxiliary pump. The auxiliary pump is configured to generate an auxiliary voltage used as a reference voltage for an integer plurality of S1 control signals.
In another embodiment, an integer number MIN1 of enabled output stages is minimized. In one embodiment, each enabled output stage is connected to the output node by using an integer plurality of U1 switches, wherein at least one control signal is used to control the charge pump stage.
In still another embodiment, the apparatus of the present invention comprising the plurality of M single charge pumps, includes an integer plurality of Q1 different configurations of single charge pumps. In one embodiment, for each configuration, each output stage is connected to the output node, and an integer plurality of C1 charge pump stages is disabled. The apparatus is adaptively tuned among the plurality of Q1 different configurations by using a plurality of control signals in order to optimize generation of the supply voltage and supply current at the output node, and to minimize a ripple voltage at the output node.